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[AK1548] AK1548 8ghz low noise integer-n frequency synthesizer 1. overview the AK1548 is an integer-n pll (phase locked loop) freq uency synthesizer, covering a wide range of frequency from 1ghz to 8ghz. consisting of a highly accurate charge pump, a reference divider, a programmable divider and a dual-modulus prescaler (p/p+1), this product provid es high performance, very low phase noise and small footprints. an idea l pll c an be ach ieve d b y combi n in g the ak15 48 w it h the exter nal l oop filter an d vco (v olt age control l ed oscillator). access to the r egi sters is c ontro ll ed vi a a 3- w i r e seria l interf ace. t he operati n g sup p l y v o lt ag e is fro m 2.7v to 3.3v, and the charge pump circuit and the serial interface can be driven by individual supply voltage. 2. features ? operating frequency : 1ghz to 8ghz ? programm abl e charge p u mp current : 650 a to 5200 a ty pical w i th 8step s the current range can be controlled by an external resistor. ? f a st lock mode for improved l o ck time : t he programm abl e timer can s w itc h t w o c h a r ge pum p current setting. ? supp l y v o lt ag e : 2.7 to 3.3 v (pvdd, a v dd pi ns) ? separate charge pump power supply : pvdd to 5.5v (cpvdd pin) ? exce ll ent phas e nois e : -226 dbc/hz ? on-chip l o ck d e tection fe atur e of pll : select a b le p h ase f r eq ue ncy d e tector (p f d ) output o r digit a l filtere d l o ck detect ? package : 20pin qfn (0.5mm pitch, 4mm 4mm 0.75mm) ? operatin g temperatur e : -40c to 85 c ms136 4-e-00 1 2012/1 http://
[AK1548] - table of contents - 1. overview ____________________________________________________________________________ 1 2. features ____________________________________________________________________________ 1 3. block diagram _______________________________________________________________________ 3 4. pin functional description and assignments _____________________________________________ 4 5. absolute maximum ratings ____________________________________________________________ 6 6. recommended operating range ________________________________________________________ 6 7. electrical characteristics ______________________________________________________________ 7 8. block functional descriptions _________________________________________________________ 11 9. register map _______________________________________________________________________ 19 10. function description - registers _______________________________________________________ 21 11. ic interface schematic _______________________________________________________________ 31 12. recommended connection schematic of off-chip component _____________________________ 33 13. block power-up timing chart (recommended flow) ______________________________________ 36 14. frequency change timing chart (recommended flow) ____________________________________ 38 15. typical evaluation board schematic ____________________________________________________ 39 16. outer dimensions ___________________________________________________________________ 40 17. marking ____________________________________________________________________________ 41 in this specification, the following notations ar e used for specific signal and register names. [name] : pin name : register group name (address name) {nam e} : reg i ster b i t n a me ms136 4-e-00 2 2012/1
[AK1548] 3. block diagram cp p h a se fr e q e n c y de t e c t o r refin + - pr es c al e r 8 / 9,1 6 /17 , 32 / 3 3, 6 4 /65 programable counter 13 bit lock detect rf i n p rfinn cpvdd cpvss av d d vref2 av ss pvss ld cl k da t a le re g i s t e r 24 b i t n divider fa st counter pdn test2 test1 r c o u n t e r 1 4 bi t bias ch a r g e pu m p swallow counter 6 bit vref1 pvdd vb g ld o ms136 4-e-00 3 2012/1
[AK1548] 4. pin functional description and assignments 1. pin functions no. name i/o pin functions power down (note 1) remarks 1 cpvss g charge pump ground 2 test1 di test pin 1 internal pull-dow n , schmidt trigger input 3 avss g analog ground 4 rfinn ai complementary input to the rf prescaler 5 rfinp ai input to the rf prescaler 6 avdd p power supply for analog blocks 7 vref1 ao connect reference voltage capacitor for ldo ?low? 8 refin ai reference signal input 9 pvss g peripherals ground 10 test2 di test pin 2 internal pull-dow n , schmidt trigger input 11 pdn di power down 12 clk di serial clock input schmidt trigger input 13 data di serial data input schmidt trigger input 14 le di load enable input schmidt trigger input 15 ld do lock detect output ?low? 16 pvdd p power supply for peripherals 17 vref2 ao connect reference voltage capacitor ?low? 18 cpvdd p power supply for charge pump 19 bias aio resistance pin for setting charge pump current 20 cp ao charge pump output ?hi-z? note 1) ?power down? means the state of [pdn]=?low? after power on. note 2) the exposed pad at the center of the backside should be connected to ground. the following table shows the meaning of ab breviations used in the ?i/o? column. ai: analog input pin ao: analog output pin aio: analog i/o pin di: digital input pin do: digital output pin p: power supply pin g: ground pin ms136 4-e-00 4 2012/1
[AK1548] 2. pin assignments 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 to p vi e w c pvss t est 1 a v ss rf i n p rf i n n a vdd vref1 refin pvss test2 pd n cl k da t a le ld pvd d vr ef2 cp v d d bi as cp 20pin qfn (0.5mm pitch, 4mm 4mm) ms136 4-e-00 5 2012/1
[AK1548] 5. absolute maximum ratings parameter symbol min. max. unit remarks vdd1 -0.3 3.6 v [avdd], [pvdd] (note 1) supply voltage vdd2 -0.3 6.5 v [cpvdd] (note 1) vss1 0 0 v [avss], [pvss] ground level vss2 0 0 v [cpvss] analog input voltage vain vss1-0.3 vdd1+0.3 v [rfinn], [rfinp], [refin] (notes 1 & 2) digital input voltage vdin vss1-0.3 vdd1+0.3 v [clk], [da t a] , [le], [pdn], [ t est 1] , [test2] (notes 1 & 2) input current iin -10 10 ma storage temperature tstg -55 125 c note 1) 0v referenc e for all vo lt ages. note 2) maximum must not be over 3. 6v . exceeding these maximum ratings may result in damage to the AK1548. normal operation is not guaranteed at these extremes. 6. recommended operating range parameter symbol min. typ. max. unit remarks operating temperature ta -40 85 c vdd1 2.7 3.0 3.3 v applied to the [avdd],[pvdd] pins supply voltage vdd2 vdd1 5.0 5.5 v applied to the [cpvdd] pin note 1) vdd1 a nd vd d2 can b e driv en in divi du all y w i t h in th e rec o mmen ded op eratin g ran ge. note 2) all spec ificatio ns are ap plic ab le w i thi n the r e comme nde d operatin g ra n ge (operati ng t e mperature / supp l y v o lt ag e ) . ms136 4-e-00 6 2012/1
[AK1548] 7. electrical characteristics 1. digital dc characteristics parameter symbol conditions min. typ. max. unit remarks high level input voltage vih 0.8 vdd1 v note 1) low level input voltage vil 0.2 vdd1 v note 1) high level input current 1 iih1 vih = vdd1=3.3v -1 1 a note 2) high level input current 2 iih2 vih = vdd1=3.3v 17 33 66 a note 3) low level input current iil vil = 0v, vdd1=3.3v -1 1 a note 1) high level output voltage voh ioh = -500 a vdd1-0.4 v note 4) low level output voltage vol iol = 500 a 0.4 v note 4) note 1) appl ied to the [ clk ], [ da t a ], [ le ], [ pdn ], [ t e st 1 ] and [ t e st 2 ] pins. note 2) appl ied to the [ clk ], [ da t a ], [ le] and [ pdn ] pins. note 3) appl ied to the [ t e st 1 ] and [ t e st 2 ] pins. note 4) appl ied to the [ ld ] pin. ms136 4-e-00 7 2012/1
[AK1548] 2. serial interface timing le ( i nput ) cl k ( i nput ) da t a ( i nput ) ts u thd tcsu d21 d20 6 d2 a0 a1 d0 d1 tch tc l tle su tle serial interface timing chart serial interface timing parameter symbol min. typ. max. unit remarks clock l level hold time tcl 25 ns clock h level hold time tch 25 ns clock setup time tcsu 10 ns data setup time tsu 10 ns data hold time thd 10 ns le setup time tlesu 10 ns le pulse width tle 25 ns ms136 4-e-00 8 2012/1
[AK1548] 3. analog circuit characteristics the resistance of 27k ? is connected to the [bias] pin. vdd1 2.7v to 3.3v, vdd2=vdd1 to 5.5v,?40c ta 85c, unless otherwise specified. parameter min. typ. max. unit remarks rf characteristics input sensitivity -5 5 dbm input frequency 1000 8000 mhz refin characteristics 0.4 vdd1 vpp refin 200mhz input sensitivity 0.4 2 vpp refin>200mhz input frequency 10 300 mhz maximum allowable prescaler output frequency 300 mhz phase detector phase detector frequency 104 mhz charge pump charge pump maximum value 5200 a charge pump minimum value 650 a icp tri-state leak current 1 na 0.7 vcpo vdd2-0.7, ta=25c vcpo : cp terminal voltage mismatch bet w e e n source and si nk curr ent s (note 1) 10 % vcpo=vdd2/2, ta=25c icp vs. vcpo (note 2) 15 % 0.5 vcpo vdd2-0.5, ta=25c regulator vref1 rise time 10 ms con nect 47 0n f cap a cit anc e at vref2 pin vref2 rise time 10 ms con nect 470 nf cap a cit a n c e at vref2 pin current consumption idd1 10 a [pdn]=?0? idd2 16 26 ma [pdn]=?1?, {pd}=0, idd for vdd1 idd3 (note 4) 0.8 1.6 ma [p dn]=?1?, {pd}=0, idd for vdd2 idd4 0.55 0.9 ma [pdn]=?1?, {pd}=1, idd for vdd1 note 1) mismatch between source and sink currents : [(|isink|-|isource|)/{(|isink|+|isource|)/2}] 100 [%] note 2) see ?charge pump characteristics - voltage vs. current?. vcpo is the output voltage at [cp]. icp vs. vcpo : [{1/2 ( | i1 |- |i2 | )}/ {1/2 ( | i1 |+ | i 2 | )} ] 100 [%] ms136 4-e-00 9 2012/1
[AK1548] note 3) when [pdn] is ?1?, the total power supply cu rrent of the AK1548 is ?idd2 +idd3+ charge pump current?. note 4) t he current depen din g on ph ase detector f r equ enc y isn ? t inclu ded. idd3 is t he st ationar y curre nt that charge pump circuit consumes. resist an ce co n n ected to th e bi a s p i n fo r settin g ch arg e pu mp ou tpu t cu rren t parameter min. typ. max. unit remarks bias resistance 22 27 33 k ? isi n k i s our c e vcpo ic p cpvdd- 0 . 5 c pvdd/ 2 0. 5 i1 i1 i2 i2 charge pump characteristics - voltage (vcpo) vs. current (icp) ms136 4-e-00 10 2012/1
[AK1548] 8. block functional descriptions 1. frequency setup the following formula is used to calculate the frequency setting for the AK1548. frequency setting (external vco output frequency) = f pfd x n where : n : dividing number n = [ (p x b) + a ] f pfd : phase detector frequency f pfd = [refin] pin input frequency / r counter dividing number p : prescaler v a l ue (see < addr ess2> : {pre[1:0]}) b : b (programmabl e) count er valu e (see < a d d ress1> : {b[12: 0]}) a : a (s w a ll o w ) c ounter va lu e (see < address 1 > : {a[5:0]}) calculation example the output frequency of external refe rence frequency oscillator is 10mhz, and f pfd is 1mhz and vco frequency is 7400mhz. AK1548 setting : r (refere n ce c ounter)= 1 0 0 0 0 000/1 0 0 000 0 = 10 (< address0 > : {r[13:0]}= ?10?) p=32 (:{pre[1:0]}=?10bin?) b=231 (:{b[12:0]}=?231?) a=8 (:{a[5:0]}=?8?) f r eque nc y s e tting = 1m [ (3 2 231) + 8] = 7400m hz lower limit for setting consecutive dividing numbers in the AK1548, it is not possible to set cons ecutive dividing numbers below the lower limit. (the lower limit is determined by a dividing number set for the prescaler.) the following table shows an example where consecutive di viding numbers below the lower limit cannot be set. the consecutive dividing numbers can be set when b p-1. ms136 4-e-00 11 2012/1
[AK1548] p=8 (dual modulus prescaler 8/9) p b[12:0] a[5:0] n [ (pb) + a ] remarks 8 6 6 54 55 cannot be set as an n divider. 8 7 0 56 this is the lower limit. 56 or over can consecutively be set as an n divider. 8 7 1 57 ? ? ? ? 8 100 9 809 ? ? ? ? 8 8191 62 65590 8 8191 63 65591 p=16 (dual modulus prescaler 16/17) p b[12:0] a[5:0] n [ (pb) + a ] remarks 16 14 14 238 239 cannot be set as an n divider. 16 15 0 240 this is the lower limit. 240 or over can consecutively be set as an n divider. 16 15 1 241 ? ? ? ? 16 4099 7 65591 ? ? ? ? 16 8191 62 131118 16 8191 63 131119 p=32 (dual modulus prescaler 32/33) p b[12:0] a[5:0] n [ (pb) + a ] remarks 32 30 30 990 991 cannot be set as an n divider. 32 31 0 992 this is the lower limit. 992 or over can consecutively be set as an n divider. 32 31 1 993 ? ? ? ? 32 4097 15 131119 ? ? ? ? 32 8191 62 262174 32 8191 63 26217 5 ms136 4-e-00 12 2012/1
[AK1548] p=64 (dual modulus prescaler 64/65) p b[12:0] a[5:0] n [ (pb) + a ] remarks 64 62 62 4030 4031 cannot be set as an n divider. 64 63 0 4032 this is the lower limit. 4032 or over can consecutively be set as an n divider. 64 63 1 4033 ? ? ? ? 64 4096 31 26217 5 ? ? ? ? 64 8191 62 524286 64 8191 63 524287 ms136 4-e-00 13 2012/1
[AK1548] 2 charge pump, loop filter the current setting of charge pump and loop filter can switch with the built-in timer for fast lock. c2 ph a s e d e t e c t o r up down tim er vco lo op f i lt er c1 c3 r2 r3 cp loop filter schematic the charge pump current for normal operation (cp1) is de termined by the setting in {c p1[2:0]}, which is a 3-bit address of {d[15:13]} in and a value of the re sistance connected to the [bias] pin. the charge pump current for the fast lock up mode operation (cp2) is dete rmined by the setting in {cp2[2:0]}, which is a 3-bit address of d[18:16] in and a value of the resistance connected to the [bias] pin. the following formula shows the relationship among the re sistance value, the register setting and the electric current value. charge pump minimum current (icp_min) [a] =17.46 / resistance connected to the bias pin [ ? ] charge pump current (icp) [a] = icp_min [a] ({cp1} or {cp2} setting +1) the allowed value range for the resistance connec ted to the [bias] pin is from 22 to 33k ? for both normal and fast lock up mode operations. ms136 4-e-00 14 2012/1
[AK1548] 3. fast lock up mode setting {fast[1:0]} in to ?11bin? and {cpgain} in to ?1? enables the fast lock up mode for the AK1548. the fast lock up mode is enabled only during the time per iod set by the timer accordi ng to the counter value in {timer[3:0]} in . the charge pump current is set to the value specified by {cp2}. when the specified time period elapses, the fast lock up mode operation is switched to the normal operation, and {cpgain} in is reset to ?0?. {timer[3:0]} in is used to set the time period fo r this mode. the following formula is used to calculate the time period : switchover time = 1 /f pfd counter value counter value = 3 + (timer[3:0] setting 4) fast lock up cp2 on normal normal cp1 off cp1 off o pe r atio n m od e c h a r ge p u m p cur r ent loop filter switch frequency setting write ?1? into {cpgain} in . fast loc k u p t im e s p ecified b y the timer f ast lo ck up mo d e t i min g c h art ms136 4-e-00 15 2012/1
[AK1548] 4 lock detect lock d e tect out put can be s e l e cted b y {ld[2: 0]} in < a d d re ss 2> . w hen {ld } is set to ?1 01b in", the ph ase detector output s an un mani pul ated p hase detecti on (c omp a ris on) result. (t his is calle d ?ana log lo ck detect?.) w hen {ld} is set to ?001bi n ?, the lock detect signa l is outp u t accordin g to the on-c h ip l o g i c. (t his is calle d ?dig it al lock d e tect?.) t he lock detect can be d one a s follo w i ng: the [ld] pin is in unlocked state (which outputs ?low?) when a frequency setup is made. in the digital lock detect, the [ld] pin outputs ?high? (w hich means the locked state) when a phase error smaller than a cycle of [refin] clock (t) is detected for n time s consecutively. when a phase error larger than t is detected for n times consecutively wh ile the [ld] pin outputs ?high?, then the [ld] pin outputs ?low? (which means the unlocked state). the counter value n can be set by {ldp} in . the n is different between ?unlocked to locked? and ?locked to unlocked?. {ldp} unlocked to locked locked to unlocked 0 n=15 n=3 1 n=31 n=7 the lock detect signal is shown below: reference clock this is ignored because it cannot be sampled. valid p f d f r eq u e nc y s ig n a l div ide d c lo c k of r f i np u t s ign al pfd o u tpu t s i gn al ignored valid i g nored ld output t h e [ ld ] pin out p ut s h i g h w hen a phas e e rro r s m al l e r t han t i s de tec t ed f or n t i m e s c on s ec ut i v e l y . case of ?r = 1? reference clock this is ignored because it cannot be sampled. valid p f d f r equen c y s i gnal d i v i ded c l oc k of r f i nput s i gnal pfd output signal ignored va li d ignored ld output the [ l d ]p i n o u t p u t s h i g h w h e n a ph as e er r o r s m a l l er t h an t i s d et e c t ed f or n t i m es c ons ec u t i v el y . case of ?r > 1? dig i t a l l o ck detect o p eratio n s ms136 4-e-00 16 2012/1
[ AK1548] phase error < t flag = flag+1 lock ([ld]=high) unlock ([ld]=low) y es no flag > n flag=0 y es no un lo ck to lo ck op eratio n flo w phase error > t y es flag=0 flag = flag+1 flag > n no y es unlock ([ld]=low) no lock ([ld]=high) address2 write lock to unlock operation flow ms136 4-e-00 17 2012/ 1
[ AK1548] 5 reference counter t he ref e rence inp u t can be s e t w i t h a div i di ng num ber i n t he ran ge of 1 t o 163 83 us in g {r [ 13: 0] }, w h i c h is a n 14-bit address of {d[13:0]} in . 0 cannot be set as a dividing number. 6 prescaler the dual modulus prescaler (p/p+1) and the swallow counter are used to provide a large dividing ratio. the prescaler is set by {pre[1:0]}, which is a 2-bit latch of {d[21:20]} in . {pre[1:0]}=?00bin?, p=8, dual modulus prescaler 8/9 {pre[1:0]}=?01bin?, p=16, dual modulus prescaler 16/17 {pre[1:0]}=?10bin?, p=32, dual modulus prescaler 32/33 {pre[1:0]}=?11bin?, p=64, dual modulus prescaler 64/65 the maximum prescaler output frequency is 300mhz. p should be set as ?rf input frequency /p 300mhz?. 7 power-down and power-save mode it is possible to operate in the power-down or power-save mode if necessary by using the external control pin. power on follo w t h e po w e r-up se qu enc e. normal operation [pdn] {pd2} {pd1} function ?low? x x power down ?high? x 0 normal operation ?high? 0 1 vbg & ldo : power up synthesizer circuits : asynchronous power down ?high? 1 1 vbg & ldo : power up synthesizer circuits : synchronous power down x : d o n ? t c a r e ms136 4-e-00 18 2012/ 1
[ AK1548] 9. register map name data address r counter 0 0 n counter (a and b) 0 1 function 1 0 initialization d21 - d0 1 1 name d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 addr ess r count 0 0 0 ldp 0 0 low noise 0 r [13] r [12] r [11] r [10] r [9] r [8] r [7] r [6] r [5] r [4] r [3] r [2] r [1] r [0] 0x0 n count 0 0 cp gain b [12] b [11] b [10] b [9] b [8] b [7] b [6] b [5] b [4] b [3] b [2] b [1] b [0] a [5] a [4] a [3] a [2] a [1] a [0] 0x1 func. pre [1] pr e [0] pd2 cp 2 [2] cp 2 [1] cp2 [0] cp1 [2] cp1 [1] cp 1 [0] ti m e r [3] ti m e r [2] ti m e r [1] ti m e r [0] fast [1] fast [0] cp hiz cp pola ld [2] ld [1] ld [0] pd1 cntr rst 0x2 initial. pre [1] pr e [0] pd2 cp 2 [2] cp 2 [1] cp2 [0] cp1 [2] cp1 [1] cp 1 [0] ti m e r [3] ti m e r [2] ti m e r [1] ti m e r [0] fast [1] fast [0] cp hiz cp pola ld [2] ld [1] ld [0] pd1 cntr rst 0x3 ms136 4-e-00 19 2012/ 1
[ AK1548] notes for writing into registers after powers on AK1548, the initial register value is not defined. it is required to write the data in all addresses in order to commit it. [examples of writing into registers] (ex. 1) power-on - bring [pdn] to ?0 (low)? - apply vdd - program address0, address1 and address2 - bring [pdn] to ?1 (high)? - program {pd1} in address 2 to ?0? (ex. 2) changing frequency settings : initialization - program address3 - program address1 (ex. 3) changing frequency settings : counter reset - program addr e ss2. as p a rt o f t h is, load ?1? t o bot h {pd 1 } a nd {cnt r_rs t } . - program address1 - program addr e ss2. as p a rt o f t h is, load ?0? t o bot h {pd 1 } a nd {cnt r_rs t } . (ex. 4) changing frequency settings : pdn pin method - bring [pdn] to ?0 (low)? - program address1 - bring [pdn] to ?1 (high)? ms136 4-e-00 20 2012/ 1
[ AK1548] 10. function description - registers < address0 : r counter > d[21:19] d18 d[17:14] d[13:0] address 0 ldp 0 r[13:0] 00 d[21:19], d[17:14] : these bits are set to the following for normal operation d21 d20 d19 d17 d16 d15 d14 0 0 0 0 0 0 0 ldp : lock detect precision the counter value for digital lock detect can be set. d18 function remarks 15 times count unlocked to locked 0 3 times count locked to unlocked 31 times count unlocked to locked 1 7 times count locked to unlocked ms136 4-e-00 21 2012/ 1
[ AK1548] r[13:0] : reference clock division number the following settings can be selected for the reference clock division. the allowed range is 1 (1/1 division) to 16383 (1/16383 division). 0 cannot be set. the maximum frequency for f pfd is 104mhz. d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/1 division 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1/2 division 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1/3 division 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1/4 division data 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1/16381 division 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1/16382 division 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1/16383 division ms136 4-e-00 22 2012/ 1
[ AK1548] < address1 : n counter > d[21:20] d19 d[18:6] d[5:0] address 0 cpgain b[12:0] a[5:0] 01 d21, d20 : these bits are set to the following for normal operation d21 d20 0 0 cpgain : sets the charge pump current when {f ast[ 1 : 0 ] } is not ?1 1bin? : d19 function remarks 0 cp1 is enabled 1 cp2 is enabled when {f ast[ 1 : 0 ] } is ?1 1bin? : d19 function remarks 0 cp1 is enabled 1 cp2 is enabled, also timer is enabled b[12:0] : b (programmable) counter value d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec prohibited 0 0 0 0 0 0 0 0 0 0 0 1 0 2 dec prohibited 0 0 0 0 0 0 0 0 0 0 0 1 1 3 dec data 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 dec ms136 4-e-00 23 2012/ 1
[ AK1548] a[5:0] : a (swallow) counter value d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec 0 0 0 0 1 0 2 dec 0 0 0 0 1 1 3 dec data 1 1 1 1 0 1 61 dec 1 1 1 1 1 0 62 dec 1 1 1 1 1 1 63 dec * requirements for a[5:0] and b[12:0] t he dat a at a[ 5 : 0] and b[ 12: 0] must meet t he f o llo w i n g req u ir ement s: a[5:0] 0, b[12:0] 3, b[12:0] a[5:0] see ?frequency setup? in section ?block functi onal descriptions? for details of the relationship between a frequency division number n and the data at a[5:0] and b[12:0]. ms136 4-e-00 24 2012/ 1
[ AK1548] < address2 : function > d[21:20] d19 d[18:16] d[15:13] d[12:9] d[8:7] pre[1:0] pd2 cp2[2:0] cp1[2:0] timer[3:0] fast[1:0] d6 d5 d[4:2] d1 d0 address cphiz cppola ld[2:0] pd1 cntr_rst 02 pre[1:0] : selects a dividing ratio for the prescaler the prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300mhz. d21 d20 function remarks 0 0 p=8, dual modulus prescaler 8/9 0 1 p=16, dual modulus prescaler 16/17 1 0 p=32, dual modulus prescaler 32/33 1 1 p=64, dual modulus prescaler 64/65 pd2, pd1 : power down select [pdn] {pd2} {pd1} function ?low? x x power down ?high? x 0 normal operation ?high? 0 1 vbg & ldo : power up synthesizer circuits : asynchronous power down ?high? 1 1 vbg & ldo : power up synthesizer circuits : synchronous power down x : don?t care (recommended ?0?) {pd2}=1 and {pd1}=1 : synthesizer circuits powers down at the timing when the phase detector frequency signal reverses. {pd2}=0 and {pd1}=1 : synthesizer circuits goes into power down during the rise up of le signal that latches 1 into {pd1}. ms136 4-e-00 25 2012/ 1
[ AK1548] cp2[2:0] : charge pump current setting 2 cp1[2: 0] : ch arg e p u m p curren t settin g 1 ak154 8 prov id es t w o s e t t i ng f o r charg e pum p current . t h e y can be set b y {cp1} an d {cp 2 }. the following formula shows the relationship among the resistance value, the register setting and the electric current that is used for lpf band calculation (tran_icp). tran_icp [a] = icp_min [a] ({cp1} or {cp2} setting +1) char ge pum p minimum curr e n t (i cp_min)[ a] = (0.851.16415) / resistance connected to the bias pin [ohm] the following table shows the typical tran_icp for each status. t r an_i cp (t ypic al) [ u nit : a] d18 d17 d16 bias resistance d15 d14 d13 33 k ? 27 k ? 22 k ? remarks 0 0 0 450 550 675 0 0 1 900 1100 1350 0 1 0 1350 1650 2025 0 1 1 1800 2200 2700 1 0 0 2250 2750 3375 1 0 1 2700 3300 4050 1 1 0 3150 3850 4725 1 1 1 3600 4400 5400 the following formula shows the relationship among the resistance value, the register setting and the electric current that can be measured (icp). icp [a] = icp_min [a] ({cp1} or {cp2} setting +1) char ge pum p minimum curr e n t (i cp_min)[ a] = (1.16415) / resistance connected to the bias pin [ohm] the following table shows the typical tran_icp for each status. ms136 4-e-00 26 2012/ 1
[ AK1548] icp (ty p ica l ) [u n i t : a] d18 d17 d16 bias resistance d15 d14 d13 33 k ? 27 k ? 22 k ? remarks 0 0 0 529 647 794 0 0 1 1058 1293 1587 0 1 0 1587 1940 2381 0 1 1 2116 2587 3175 1 0 0 2645 3233 3968 1 0 1 3175 3880 4762 1 1 0 3704 4527 5555 1 1 1 4233 5173 6349 ms136 4-e-00 27 2012/ 1
[ AK1548] timer[3:0] : sets the switchover time for cp2-to-cp1 t h is is enable d w h en {f ast [ 1 : 0 ] } is ?1 1bin? a nd {[ cpgai n }= ?1?. t he charge p u m p current is s e t int o va lue { c p2[ 2 : 0 ] } d e si gnat e duri ng s w it c hov er t i me. i t goes t o b e {c p1 [2 :0 ]} se ttin g va lu e a f te r th e time o u t. the following formula shows the relationship between the switchover time and the counter value. switchover time = 1/ f pfd counter value counter value = 3 + timer[3:0] 4 the following table shows the relationship between counter value and {timer[3:0]}. d12 d11 d10 d9 function remarks 0 0 0 0 3 counts 0 0 0 1 7 counts 0 0 1 0 11 counts 0 0 1 1 15 counts 0 1 0 0 19 counts 0 1 0 1 23 counts 0 1 1 0 27 counts 0 1 1 1 31 counts 1 0 0 0 35 counts 1 0 0 1 39 counts 1 0 1 0 43 counts 1 0 1 1 47 counts 1 1 0 0 51 counts 1 1 0 1 55 counts 1 1 1 0 59 counts 1 1 1 1 63 counts ms136 4-e-00 28 2012/ 1
[ AK1548] fast[1:0] : enables or disables the fast lock mode when {fast[1:0]} is ?11bin?, {cpgain} of function latch is the fast lock mode bit. when fast lock is enabled, charge pump current is set to the value of {cp2} setting during the switchover time under the control of the timer counter. after the timeout, {cpgain} is reset into ?0? and charge pump current goes to be {cp1} setting value. d8 d7 {cpgain} function remarks 0 {cp1} is enabled x 0 1 {cp2} is enabled 0 {cp1} is enabled 0 1 1 {cp2} is enabled 0 {cp1} is enabled 1 1 1 {cp2} is en ab l ed, and switchover operates. {cpgain} is reset to ?0? af ter timeout. cphiz : tri-state output setting for charge pump d6 function remarks 0 charge pumps are activated. use this setting for normal operation. 1 tri-state note 1) not e 1) t he charge pu mp out put is t u rne d off and put in t he hi gh-imp e d anc e (hi-z) st at e. cppola : selects positive or negative output polarity for cp1 and cp2 d5 function remarks 0 negative 1 positive ms136 4-e-00 29 2012/ 1
[ AK1548] high high cha r ge pump outp u t v o lt a g e negati v e positi v e low lo w v co frequency ld selects output from [ld] pin d4 d3 d2 function remarks 0 0 1 digital lock detect 1 0 1 analog lock detect cntr_rst : counter reset d0 function remarks 0 normal operation 1 r and n counters are reset. < address3 : initialization > this function is same as . when this register is accessed, the following occurs : - address2 is loaded. - an internal pulse resets the r counter, n counter and {timer} settings to load-state conditions, and also charge pump to tri-state. - writing address1 activates the r and n counter , {timer} and charge pump. {timer} is enabled when {fast}=?11bin? and {cpgain}=?1?. ms136 4-e-00 30 2012/ 1
[ AK1548] 11. ic interface schematic no. pin name i/o r0( ) cur( a) function 11 pdn i 300 12 clk i 300 13 data i 300 14 le i 300 digital input pin r0 2 test1 i 300 10 test2 i 300 digital input pin (pull-down) r0 100k 15 ld o digital output pin 8 refin i 300 analog input pin r0 19 bias io 300 7 vref1 io 300 17 vref2 io 300 analog input/output pin r0 ms136 4-e-00 31 2012/ 1
[ AK1548] no. pin name i/o r0( ) cur( a) function 20 cp o analog output pin 4 rfinn i 12k 20 5 rfinp i 12k 20 analog input pin (rf input pin) r0 ms136 4-e-00 32 2012/ 1
[ AK1548] 12. recommended connection sche matic of off-chip component 1. power supply pins pvd d cpv d d ls i a vdd 100pf 10 f 0. 0 1 f 0.01 f 0.01 f 100pf 10 f 100 pf 10 f 2. vref1, vref2 vre f 1 220nf 10 % vre f 2 470nf10% lsi ms136 4-e-00 33 2012/ 1
[ AK1548] 3. test1, test2 test1,2 lsi 4. refin refin lsi 100pf10% 5. rfinp rfinn lsi rf inp vc o ou tp u t rfi n n 100 pf 1 0% 100pf10% 51 ? 6. bias ms136 4-e-00 34 2012/ 1
[ AK1548] ms136 4-e-00 35 2012/ 1 lsi bias 22k ? ~33k ?
[ AK1548] 13. block power-up timing chart (recommended flow) power-up sequence (pdn control case) note) after powers on, the initial setting of registers is undefined. it is required to write in address0, 1 and 2 to settle them. it is recommended that [pdn] pin is risen up after address2 {pd1}=1 write in. it takes about 10ms from pdn rise-up to ldo rise-up. the power-up by register ({pd1}=0 write in) should be done after ldo rise-up. address1 setting pdn register writing ldo {pd1}=0 write in 1.9v cp address0 setting 0v 10ms hi-z vdd1, vdd2 pdn should be risen u p after { pd1 } =1 write in. register value defined address2 { pd1 } =0 address2 {pd1}=1 output ms136 4-e-00 36 2012/ 1
[ AK1548] address1 settin g pdn register writing ldo cp output address0 settin g 0v 10ms hi-z vdd1,vdd2 address2 { pd1 } =0 address2 { pd1 } =1 {pd1}=0 write in undefined register value defined 1.9v power-up sequence (vdd1/vdd2/p dn simultaneous power-up) note) after powers on, the initial setting of registers is undefined. it is required to write in address0, 1 and 2 to settle them. it takes about10ms from pdn rise-up to ldo rise-up. the power-up by register ({pd1}=0 write in) should be done after ldo rise-up. ms136 4-e-00 37 2012/ 1
[ AK1548] 14. frequency change timing chart (recommended flow) high address1 settin g pdn register writing cp address0 settin g hi-z vdd1,vdd2 address2 { pd1 } =0 address2 high { pd1 } =1 output1 output2 frequency change sequence ({pd1} control) high high address1 settin g pdn register writing cp address0 settin g hi-z vdd1,vdd2 address3 { pd1 } =0 out p ut1 output2 frequency change sequence (initialization register control) note) the data on address3 is same as address2, but {pd1} should be set ?0?. writing in address3 puts cp output to hi-z. the rise-up of le signal at writing in address1, which is subsequent frequency setting up sequence, is trigger for cp output. ms136 4-e-00 38 2012/ 1
[ AK1548] typical evaluation board schematic c2 a k 1548 loop filt e r c1 c3 r2 r3 cp rfout 51 100pf rfinn vco b i as rf inp 100pf 27k re fin vref1 220nf 100pf 100pf 18 18 18 vr e f 2 470nf note1) although it is no problem that both of [test1] and [test2] are open, it is recommended that they should be connected to ground. note2) although it is no problem that exposed pad at the center of the backside is open, it is recommended that it should be connected to ground. ms136 4-e-00 39 2012/ 1
[ AK1548] ms136 4-e-00 40 2012/ 1 15. outer dimensions n o t e ) t h e expo se d p a d a t t h e cen t er o f t h e ba ckside sh ould b e conne ct e d to g r o und .
[ AK1548] ms136 4-e-00 41 2012/ 1 16. marking a. s t y l e qfn b. numb er of pins 20 c. a1 pin mark ing d. product num be r 154 8 e . da te co de ywwl (4 digits) y lo w e r 1 dig i t of calend ar ye ar (y ear 2012-> 2, 2013-> 3 ...) ww week l lot ide n t if ica t ion, give n t o e a ch pro duct lot w h ich is ma de in a w eek (a, b, c?) lot i d is given in a lp hab et ical or der (c) ywwl (e) 1548 (d)
[ AK1548] important notice z t hese products and t heir sp e c if icat io ns are subj ect t o chan ge w i t h out not i c e. w hen you con s ider an y us e or applic at ion of t hese pro duc t s , please mak e inqu iries t he sal e s of f ice of asa h i kasei micr ode vices cor porat i on (akm) or au t horize d di st rib u t o rs as t o current st at us of t he prod uct s . z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustra te the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or syst ems containing them, may require an export license or other official approval u nder the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one design ed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assu me any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. ms136 4-e-00 42 2012/ 1

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